Optical lithography hit an interesting point in the 1990’s. Once circuit paths shrank to 180nm, we hit the physical limits of what the light wavelength and the optics in the lithography system could imprint on the silicon. You simply could not print silicon circuits any smaller. This was a huge problem for chip companies.

What some clever researchers did was come up with a way to bend these limits. Circuits are printed on silicon using a mask that creates shadows where circuit lines should be, and allows UV light to mark the areas that should be cut away. What they discovered is they would modify the circuit images by adding little ‘corrections’ to the circuit paths. These corrections would cause optical interference patterns that would actually generate the smaller features in the silicon. They started with simple ‘dog ears’ at the ends of circuits. As the features got smaller and smaller, the optical tricks they used got more and more complex.

This image below shows you an example. Each of these 5 lithography pictures generates the same circuit ‘plus sign’ on the left marked ‘no correction’. However, the ones to the right are able to do so at tremendously smaller circuit sizes. The image on the far right, ILT, can only be generated using complex mathematical models that work backwards from the desired final circuit image to the mask that must be put into the lithography machine to generate it. This, however, takes a lot of compute power.

Fast forward to today, and nVidia has released GPU optimized software to compute lithography patterns. Not only that, but they released the software called cuLitho. Using GPU’s, they claim it is 40x faster and uses 1/9 the power of traditional methods to calculate the computed lithography masks